memory bus width造句
例句與造句
- DDR memory bus width per channel is 64 bits ( 72 for ECC memory ).
- It also equals number of ranks ( rows ) multiplied by DDR memory bus width.
- The 82492 is a customized high performance SRAM that supports 32-, 64-, and 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes, and optional sectoring.
- High-performance graphics cards running many interfaces in parallel can attain very high total memory bus width ( e . g ., 384 bits in the NVIDIA GeForce GTX TITAN and 512 bits in the AMD Radeon R9 290X using six and eight 64-bit interfaces respectively ).
- On 28 April 2008, Apple announced an updated iMac line featuring an 8800 GS . However, the GPU is actually a rebranded NVIDIA GeForce 8800M GTS . It features up to 512 MB of 800 MHz GDDR3 video memory, 64 unified stream processors, a 500 MHz core speed, a 256-bit memory bus width, and a 1250 MHz shader clock.
- It's difficult to find memory bus width in a sentence. 用memory bus width造句挺難的